1. Field of the Invention
The invention relates to phase-look loop architectures, and more particularly to range limited frequency centering clock recovery apparatus.
2. Description of the Related Art
In many types of signal transmission schemes, signals are transmitted as a self-clocking string of ones and zeros. That is, the string has logic level transitions occurring at least a specified number of times within a limited number of bit cells so that the data string contains a significant clock frequency component which is separable from the data information. One example of such a self-clocking data transmission scheme is the FDDI standard, which ensures at least one edge transition per 10 bit cells.
Apparatus for deriving the clock signal from such strings must effectively operate in the presence of noise and jitter, yet must be able to follow permitted frequency variations reliably. In FDDI systems, for example, the clock frequency of incoming data signals is permitted to vary by 50 ppm above or below the nominal frequency of 125MHz.
Many self-clocking communications systems, of which FDDI is one example, operate intermittently, that is, in stop-and-start applications. Packets of encoded information occur at random intervals, so there are many time intervals when a signal line is inactive and has only random or impulse noise signals present. A conventional analog phase-looked loop receiver operating under such conditions has difficulty operating because fast acquisition requires wide loop bandwidths while operation with noisy signals requires narrow loop bandwidths.
In Campbell, U.S. Pat. No. 4,565,976, there is disclosed a clock recovery apparatus using two phase-lock loops. Each loop has its own voltage controlled oscillator (VCO) with its output coupled to one input of a respective phase detector. The first phase-lock loop phase detector locks to the frequency of the system reference signal, and the phase detector output is used as a control voltage for the first phase-lock loop. This control voltage is also used as an additional control voltage in the second phase-look loop. The second phase-look loop has its own voltage controlled oscillator and phase detector, which receives the incoming data signal. The output of the second phase detector is a control voltage for the phase of the second VCO. As mentioned above, the second VCO also receives another voltage control signal from the first phase-lock loop. Thus, the second VCO receives two control signals, one constraining its frequency to be near that of the system reference signal and the second being used to control the phase and fine-tuned frequency of the second phase-lock loop to be that of the received signal. The Campbell apparatus is referred to as a type of range-limited clock recovery circuit.
The apparatus of the Campbell patent works well, but requires that the gain of the two VCOs be well matched. If the two VCOs are not sufficiently well matched, then the VCO of the first phase-lock loop may center the second phase-lock loop at a frequency which is not close enough to the clock frequency of the incoming data signal. In such a situation, the clock recovery apparatus may require longer than the maximum available time period to look onto the incoming clock frequency, or it may not be able to capture the incoming clock frequency at all. The need for well-matched VCOs places a premium on process invariance, thereby reducing yields.
In LLewellyn, et al., 1988 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 12-13 and 276-277, there is described a frequency discriminating feedback loop that regulates the VCO control voltage and thus the operating frequency, preventing unbounded variations. A reference PLL, with a VCO ring oscillator supposedly identical to that of a primary PLL, is locked to a reference frequency. A comparator block has been included to sense when the primary oscillator control current crosses current thresholds placed symmetrically above and below the reference current. If either threshold is crossed, the comparator forces a correction at the primary PLL phase comparator, preventing further VCO control voltage excursions. Like Campbell, however, this range limited circuit still uses two VCOs and for at least that reason has limitations similar to those of Campbell.